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ADuC7060
SRAM
Table 11. REMAP MMR Bit Designations
The ADuC7060 features 4 kB of SRAM, organized as 1024 ×
32 bits, that is, 1024 words located at 0x40000. The RAM space
can be used as data memory as well as volatile program space.
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide memory
array. SRAM is read/writable in 8-, 16-, and 32-bit segments.
Bit
7:1
0
Description
Reserved. These bits are reserved and should be written
as 0 by user code.
Remap bit.
Set by user to remap the SRAM to 0x00000000.
Cleared automatically after reset to remap the Flash/EE
memory to 0x00000000.
Remap
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000. It is possible to logically remap
the SRAM to Address 0x00000000 by setting Bit 0 of the remap
MMR located at 0xFFFF0220. To revert Flash/EE to 0x00000000,
Bit 0 of remap is cleared.
FLASH/EE CONTROL INTERFACE
Serial and JTAG programming use the Flash/EE control
interface, which includes the eight MMRs outlined in this
section.
FEESTA Register
FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 12.
It is sometimes desirable to remap RAM to 0x00000000 to optimize
the interrupt latency of the ADuC7060 because code can run in
full 32-bit ARM mode and at maximum core speed. Note that,
when an exception occurs, the core defaults to ARM mode.
Remap Operation
When a reset occurs on the ADuC7060, execution starts automati-
Name:
Address:
Default value:
Access:
FEESTA
0xFFFF0E00
0x0020
Read
cally in the factory programmed internal configuration code.
This so-called kernel is hidden and cannot be accessed by user
code. If the ADuC7060 is in normal mode, it executes the power-on
configuration routine of the kernel and then jumps to the reset
vector, Address 0x00000000, to execute the user’s reset exception
routine. Because the Flash/EE is mirrored at the bottom of the
memory array at reset, the reset routine must always be written
in Flash/EE.
Table 12. FEESTA MMR Bit Designations
Bit Description
15:6 Reserved.
5 Reserved.
4 Reserved.
3 Flash interrupt status bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
The remap command must be executed from the absolute Flash/EE
address and not from the mirrored, remapped segment of memory,
because this may be replaced by SRAM. If a remap operation is
executed while operating code from the mirrored location,
prefetch/data aborts can occur or the user can observe abnormal
program operation. Any kind of reset logically remaps the
Flash/EE memory to the bottom of the memory array.
Remap Register
2
1
0
register is set. Cleared when reading the FEESTA
register.
Flash/EE controller busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.
Command fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading the FEESTA register.
Command pass. Set by the MicroConverter? when a
command completes successfully. Cleared
Name:
Address:
Default value:
Remap
0xFFFF0220
0x0000
automatically when reading the FEESTA register.
FEEMOD Register
FEEMOD sets the operating mode of the flash control interface.
Table 13 shows FEEMOD MMR bit designations.
Access:
Function:
Read and write
This 8-bit register allows user code to remap
Name:
Address:
FEEMOD
0xFFFF0E04
either RAM or Flash/EE space into the bottom
of the ARM memory space starting at
Address 0x00000000.
Default value:
Access:
Rev. 0 | Page 20 of 100
0x0000
Read and write
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